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s3c9644/c9648/p9648 product overview 1- 1 1 product overview sam87ri product family samsung's sam87ri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a dual address/data bus architecture and a large number of bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. many sam87ri microcontrollers have an external interface that provides access to external memory and other peripheral devices. s3c9644/c9648/p9648 microcontroller the s3c9644/c9648/p9648 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam87ri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9644 has 4k-bytes of program memory on-chip and s3c9648 has 8k-bytes. using the sam87ri design approach, the following peripherals were integrated with the sam87ri core: ? five configurable i/o ports (32 pins) ? 20 bit-programmable pins for external interrupts ? 8-bit timer/counter with three operating modes ? low speed usb function the s3c9644/c9648/p9648 is a versatile microcontroller that can be used in a wide range of low speed usb support general purpose applications. it is especially suitable for use as a keyboard controller and is available in a 42 -pin sdip and a 44-pin qfp package. otp the s3c9644/c9648 microcontroller is also available in otp (one time programmable) version, S3P9648. S3P9648 microcontroller has an on-chip 8k-byte one-time-programmable eprom instead of masked rom. the S3P9648 is comparable to s3c9644/c9648, both in function and in pin configuration.
product overview s3 c9644/c9648/p9648 1- 2 features cpu ? sam87ri cpu core memory ? 4/8k-byte internal program memory (rom) ? 208-byte ram instruction set ? 41 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 1.0 m s at 6 mhz f osc interrupts ? 25 interrupt sources with one vector, each source has its pending bit ? one level, one vector interrupt structure oscillation circuit ? 6 mhz crystal/ceramic oscillator ? external clock source (6 mhz) general i/o ? bit programmable five i/o ports (34 pins total) ? (d+/ps2, d-/ps2 included) timer/counter ? one 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function ? one 8-bit timer/counter with compare/overflow usb serial bus ? compatible to usb low speed (1.5 mbps) device 1.0 specification. ? 1 control endpoint and 2 data endpoint ? serial bus interface engine (sie) ? packet decoding/generation ? crc generation and checking ? nrzi encod ing/decoding and bit-stuffing ? 8 bytes each receive/transmit usb buffer operating temperature range ? ? 40 _ c to + 85 _ c operating voltage range ? 4.0 v to 5.25 v package types ? 42-pin sdip ? 44-pin qfp
s3c9644/c9648/p9648 product overview 1- 3 block diagram port 0 port 3 sam87ri cpu p0.0-p0.7/int2 4/8-kb rom p3.0 p3.1 p3.2 p3.3/clo osc 208-byte register port 4 p4.0 / int1 p4.1 / int1 p4.2 / int1 p4.3 / int1 timer 0 port 1 port 2 p2.0-p2.7 / int0 p1.0-p1.7 x in x out sam87ri bus basic timer i/o port and interrupt control usb d+/ps2 d-/ps2 3.3 v out 16 bytes usb buffer figure 1-1. block diagram
product overview s3 c9644/c9648/p9648 1- 4 pin assignments p3.1 p3.0 int0 / p2.0 int0 / p2.1 int0 / p2.2 int0 / p2.3 int0 / p2.4 int0 / p2.5 int0 / p2.6 int0 / p2.7 v dd v ss x out x in test int1 / p4.0 int1 / p4.1 reset int1 / p4.2 int1 / p4.3 p1/7 s3c9644 s3c9648 42-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.2 p3.3/clo d+/ps2 d-/ps2 3.3 v out nc p0.0 / int p0.1 / int p0.2 / int p0.3 / int p0.4 / int p0.5 / int p0.6 / int p0.7 / int p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-2. pin assignment diagram (42-pin sdip package)
s3c9644/c9648/p9648 product overview 1- 5 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p4.3/int1 p4.2/int1 reset 3.3 v out d-/ps2 d+/ps2 p3.3/clo p3.2 p3.1 p3.0 p2.0/int0 p2.1/int0 p2.2/int0 p2.3/int0 nc nc nc p0.0/int2 p0.1/int2 p0.2/int2 p0.3/int2 p0.4 /int2 p0.5/int2 p0.6/int2 p0.7/int2 int0 / p2.4 int0 / p2.5 int0 / p2.6 int0 / p2.7 v dd v ss x out x in test p4.0/int1 p4.1/int1 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 s3c9644 s3c9648 44-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 figure 1-3. pin assignment diagram (44-pin qfp package)
product overview s3 c9644/c9648/p9648 1- 6 pin descriptions table 1-1. s3c9644/c9648/p6408 pin descriptions pin names pin type pin description circuit number pin numbers share pins p0.0-p0.7 i/o bit-programmable i/o port for schmitt trigger input or open-drain output. port0 can be individually configured as external interrupt inputs. pull-up resistors are assignable by software. b 36-29 (30-23) int2 p1.0-p1.7 i/o bit-programmable i/o port for schmitt trigger input or open-drain output. pull-up resistors are assignable by software. b 28-21 (22-15) ? p2.0-p2.7 i/o bit-programmable i/o port for schmitt trigger input or open-drain output. port2 can be individually configured as external interrupt inputs. pull-up resistors are assignable by software. b 3-10 (41-44, 1-4) int0 p3.0-p3.3 i/o bit-programmable i/o port for schmitt trigger input, open-drain or push-pull output. p3.3 can be used to system clock output(clo) pin. c 2, 1, 42, 41 (40-37) p3.3/cl o p4.0-p4.3 i/o bit-programmable i/o port for schmitt trigger input or open-drain output or push-pull output. port4 can be individually configured as external interrupt inputs. in output mode, pull-up resistors are assignable by software. but in input mode, pull-up resistors are fixed. d 16, 17, 19, 20 (10, 11, 13, 14) int1 d+/ps2 d-/ps2 i/o programmable port for usb interface or ps2 interface. ? 40-39 (36-35) ? 3.3 v out ? 3.3 v output from internal voltage regulator ? 38 (34) ? x in , x out ? system clock input and output pin (crystal/ceramic oscillator, or external clock source) ? 14, 13 (8, 7) ? int0 int1 int2 i external interrupt for bit-programmable port0, port2 and port4 pins when set to input mode. ? 3-10, 16,17, 19, 20, 29-36 (30-23, 41-44, 1-4, 10, 11, 13, 14) port2/ port4/ port0 reset i reset signal input pin. input with internal pull-up resistor. a 18 (12) ? test i test signal input pin (for factory use only; connected to v ss ) ? 15 (9) ? v dd ? power input pin ? 11 (5) ? v ss ? ground input pin ? 12, (6) ? nc ? no connection ? 37 (31,32, 33) ? note: pin numbers shown in parenthesis '( )' are for the 44-qfp package; others are for the 42-sdip package.
s3c9644/c9648/p9648 product overview 1- 7 pin circuits table 1-2. pin circuit assignments for the s3c9644/c9648/p6408 circuit number circuit type s3c9644/c9648/p6408 assignments a i reset signal input b i/o ports 0, 1, and 2 c i/o port 3 d i/o port 4 v dd pull-up resistor in noise filter figure 1-4. pin circuit type a (reset) output disable in put data mux d0 d1 mode in put data in put out put d0 d1 i/o pull-up enable v ss v dd pull-up resistor output data figure 1-5. pin circuit type b (ports 0, 1 and 2)
product overview s3 c9644/c9648/p9648 1- 8 v dd open drain output disable in put data mode in put data in put out put d0 d1 i/o output data v ss mux d0 d1 figure 1-6. pin circuit type c (port 3)
s3c9644/c9648/p9648 product overview 1- 9 v dd open drain output disable in put data mode in put data in put out put d0 d1 i/o output data v ss pull-up enable v dd pull-up resistor mux d0 d1 figure 1-7. pin circuit type d (port 4)
product overview s3 c9644/c9648/p9648 1- 10 application circuit x out keyboard matrix 0 1 2 3 15 0 1 2 3 7 x in v ss1 v dd 5v port 3 port 0 port 1 port 2 reset h o s t dp dm s3c9644 s3c9648 S3P9648 5v port 4 d+/ps2 d-/ps2 note : port4 can use expend keyboard matrix. d+/ps2, d-/ps2 can use ps2 keyboard interface (see ps2conint, page 4-25). port 4.2, 4.3 can use ps2 mouse interface. port 3 can use led direct drive. figure 1-8. keyboard application circuit diagram
s3c9644/c9648/p9648 address spaces 2- 1 2 address spaces overview the s3c9644/c9648/p9648 microcontroller has two kinds of address space: ? program memory (rom), internal ? internal register file a 13-bit address bus supports both program memory. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9644 has 4k-bytes of mask-programmable program memory on-chip and s3c9648 has 8k-bytes. there is one program memory configuration option: ? internal rom mode, in which only the 8k-byte internal program memory is used. the s3c9644/c9648/p9648 microcontroller has 208 general-purpose registers in its internal register file. twenty- seven bytes in the register file are mapped for system and peripheral control functions.
address sapces s3c9 644/c9648/p9648 2- 2 program memory (rom) normal operating mode (internal rom) the s3c9644 has 4k-bytes (locations 0h?0fffh) of internal mask-programmable program memory. the s3c9648/p9648 has 8k-bytes (locations 0h?1fffh) of internal mask-programmable program memory. the first 2 bytes of the rom (0000h?0001h) are an interrupt vector address. the program reset address in the rom is 0100h. (decimal) (hex) 1fffh (s3c9648/p9648) 8,191 2 1 0 0002h 0001h 0000h interrupt vector 8 k-byte internal program memory area 256 program start 0100h 4 k-byte internal program memory area 0 fffh (s3c9644) 4,095 figure 2-1. program memory address space
s3c9644/c9648/p9648 address spaces 2- 3 register architecture the upper 64 bytes of the s3c9644/c9648/p9648's internal register file are addressed as working registers, system control registers and peripheral control registers. the lower 192 bytes of internal register file (00h?bfh) is called the general purpose register space . the total addressable register space is thereby 256 bytes. 233 registers in this space can be accessed.; 208 are available for general-purpose use. for many sam87ri microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00h?bfh). this register file expansion is not implemented in the s3c9644/c9648/p9648, however. page addressing is controlled by the system mode register (sym.1?sym.0). the specific register types and the area (in bytes) that they occupy in the internal register file are summarized in table 2-1. table 2-1. register type summary register type number of bytes cpu and system control registers 11 peripheral, i/o, and clock control and data registers 34 general-purpose registers (including the 16-bit common working register area) 208 total addressable bytes 253
address sapces s3c9 644/c9648/p9648 2- 4 working registers e0h c0h cfh dfh d0h bfh 00h ffh system control registers general purpose register file and stack area 192 bytes 64 bytes of common area peripheral control registers figure 2-2. internal register file organization
s3c9644/c9648/p9648 address spaces 2- 5 common working register area (c0h?cfh) the sam87ri register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this 16-byte address range is called common area . that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. however, because the s3c9644/c9648/p9648 uses only page 0, you can use the common area for any internal data operation. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb lsb rn rn + 1 n = even address figure 2-3. 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. examples: 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) r3 + 45h
address sapces s3c9 644/c9648/p9648 2- 6 system stack s3c9-series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9644/c9648/p9648 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-4. stack contents after a call instruction pch pcl high address pch top of stack pcl flags stack contents after an interrupt top of stack low address figure 2-4. stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9644/c9648/p9648, the sp must be initialized to an 8-bit value in the range 00h?bfh. note: in case a stack pointer is initialized to 00h, it is decreased to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
s3c9644/c9648/p9648 address spaces 2- 7 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0c0h ; sp c0h (normally, the sp is set to 0c0h by the ; initialization routi ne) ? ? ? push sym ; stack address 0bfh sym push clkcon ; stack address 0beh clkcon push 20h ; stack address 0bdh 20h push r3 ; stack address 0bch r3 ? ? ? pop r3 ; r3 stack address 0bch pop 20h ; 20h stack address 0bdh pop clkcon ; clkcon stack address 0beh pop sym ; sym stack address 0bfh
s3c9644/c9648/p9648 addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam87ri instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam87ri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? relative address (ra) ? immediate (im)
addressing modes s3 c9644/c9648/p9648 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3-1). working register addressing differs from register addressing because it uses an 16 -byte working register space in the register file and an 4-bit register within that space (see figure 3-2). program memory dst opcode 8-bit register file address one-operand instruction (example) register file operand points to one register in register file value used in instruction execution sample instruction: dec cntr ; where cntr is the label of an 8-bit register address figure 3-1. register addressing sample instruction: add r1,r2 ; where r1=c1h and r2=c2h program memory dst opcode 4-bit working register two- operand instruction (example) points to the working register (1 of 16) operand 4 lsbs src . . . . cfh c0h register file figure 3-2. working register addressing
s3c9644/c9648/p9648 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3-3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. 8-bit register file address one-operand instruction (example) points to one register in register file register file operand program memory dst opcode address address of operand used by instruction value used in instruction execution sample instruction: rl @shift ; where shift is the label of an 8-bit register address figure 3-3. indirect register addressing to register file
addressing modes s3 c9644/c9648/p9648 3- 4 indirect register addressing mode (c ontinued ) program memory example instruction references program memory points to register pair register file 16-bit address points to program memory operand value used in instruction program memory pair register dst opcode sample instructions: call @rr2 jp @rr2 figure 3-4. indirect register addressing to program memory
s3c9644/c9648/p9648 addressing modes 3- 5 indirect register addressing mode (c ontinued ) program memory dst opcode 4-bit working register address points to the working register (1 of 16) 4 lsbs src sample instruction: or r6,@r2 operand value used in instruction operand . . . . cfh c0h register file figure 3-5. indirect working register addressing to register file
addressing modes s3 c9644/c9648/p9648 3- 6 indirect register addressing mode (c oncluded ) sample instructions: ldc r5,@rr2 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4,r8 ; external data memory access next 3 bits point to working register pair (1 of 8) operand value used in instruction 4-bit working register address example instruction references either program memory or data memory program memory opcode dst src 16-bit address points to program memory or data memory program memory or data memory lsb selects . . . . cfh c0h register file register pair figure 3-6. indirect working register addressing to program or data memory
s3c9644/c9648/p9648 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8). for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. points to one of the working registers (1 of 16) value used in instruction two- operand instruction example program memory opcode dst 4 lsbs register file operand index x(offset) + sample instruction: ld r0,#base[r1] ; where base is an 8-bit immediate value ~ ~ ~ ~ src figure 3-7. indexed addressing to register file
addressing modes s3 c9644/c9648/p9648 3- 8 indexed addressing mode (c ontinued ) next 3 bits 4-bit working register address program memory + operand register pair 16-bit address added to offset lsb selects 8 bits 16 bits 16 bits value used in instruction program memory or data memory point to working register pair (1 of 8) sample instructions: ldc r4,#04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. opcode dst xs(offset) src register file figure 3-8. indexed addressing to program or data memory with short offset
s3c9644/c9648/p9648 addressing modes 3- 9 indexed addressing mode (c oncluded ) next 3 bits 4-bit working register address program memory opcode dst xl l (offset) + register file operand register pair 16-bit address added to offset lsb selects 16 bits 16 bits 16 bits value used in instruction program memory or data memory point to working register pair (1 of 8) xl h (offset) sample instructions: ldc r4,#1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. src figure 3-9. indexed addressing to program or data memory with long offset
addressing modes s3 c9644/c9648/p9648 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. memory address used lsb selects program memory or data memory: "0" = program memory "1" = data memory program or data memory upper addr byte lower addr byte dst / src opcode "0" or "1" program memory sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. figure 3-10. direct addressing for load instructions
s3c9644/c9648/p9648 addressing modes 3- 11 direct address mode (c ontinued ) program memory next opcode lower addr byte program memory address used upper addr byte opcode sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address figure 3-11. direct addressing for call and jump instructions
addressing modes s3 c9644/c9648/p9648 3- 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. program memory program memory address used displacement opcode signed displacement value + current pc value current instruction next opcode sample instruction: jr ult,$+offset ; where offset is a value in the range +127 to ?128 figure 3-12. relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. program memory (the operand value is in the instruction) opcode operand sample instruction: ld r0,#0aah figure 3-13. immediate addressing
s3c9644/c9648/p9648 control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c9644/c9648/p9648 control registers are presented in an easy-to- read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4-1. figure 4-1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s 3c9644/c9648/p9648 4- 2 table 4-1. system and peripheral control registers register name mnemonic decimal hex r/w timer 0 counter register t0cnt 208 d0h r timer 0 data register t0data 209 d1h r/w timer 0 control register t0con 210 d2h r/w location d3h is not mapped. clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w locations d6h-d7h are not mapped. port 0 interrupt control register p0int 216 d8h r/w stack pointer sp 217 d9h r/w port 0 interrupt pending register p0pnd 218 dah r/w location dbh is not mapped. basic timer control register btcon 220 dch r/w basic timer counter register btcnt 221 ddh r location deh is not mapped. system mode register sym 223 dfh r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 4 data register p4 228 e4h r/w port 3 control register p3con 229 e5h r/w port 0 control register (high byte) p0conh 230 e6h r/w port 0 control register (low byte) p0conl 231 e7h r/w port 1 control register (high byte) p1conh 232 e8h r/w port 1 control register (low byte) p1conl 233 e9h r/w port 2 control register (high byte) p2conh 234 eah r/w port 2 control register (low byte) p2conl 235 ebh r/w port 2 interrupt control register p2int 236 ech r/w port 2 interrupt pending register p2pnd 237 edh r/w port 4 control register p4con 238 eeh r/w port 4 interrupt enable/pending register p4intpnd 239 efh r/w
s3c9644/c9648/p9648 control registers 4- 3 table 4-1. system and peripheral control registers (continued) register name mnemonic decimal hex r/w usb function address register faddr 240 f0h r/w control endpoint status register ep0csr 241 f1h r/w interrupt endpoint 1 control status register ep1csr 242 f2h r/w control endpoint byte count register ep0bcnt 243 f3h r control endpoint fifo register ep0fifo 244 f4h r/w interrupt endpoint 1 fifo register ep1fifo 245 f5h w usb interrupt pending register usbpnd 246 f6h r/w usb interrupt enable register usbint 247 f7h r usb power management register pwrmgr 248 f8h r/w interrupt endpoint 2 control status register ep2csr 249 f9h r/w interrupt endpoint 2 fifo register ep2fifo 250 fah w usb/ps2 mode select register usbsel 251 fbh r/w d+/ps2, d-/ps2 data register (only ps2 mode) ps2data 252 fch r/w ps2 control and interrupt pending register ps2conint 253 fdh r/w usb tranceiver crossover point control register xcon 254 feh r/w usb reset register usbrst 255 ffh r/w
control registers s 3c9644/c9648/p9648 4- 4 flags - system flags register d5h bit identifier reset reset value read/write .7 .6 carry flag (c) 0 1 operation does not generate a carry or borrow condition operation generates carry-out or borrow into high-order bit 7 register mnemonic full register name register address (hexadecimal) bit number: msb = bit 7 lsb = bit 0 r w r/w '?' = = = = read-only write-only read/write not used bit number(s) that is/are appended to the register name for bit addressing description of the effect of specific bit settings name of individual bit or bit function addressing mode or modes you can use to modify register values .7 .6 .5 .4 .3 .2 .1 .0 x x x x x x 0 0 r/w r/w r/w r/w r/w r/w r/w r/w not used undetermined value logic zero logic one '?' 'x' '0' '1' = = = = reset value notation: zero flag (z) 0 1 operation result is a non-zero value operation result is zero sign flag (s) 0 1 operation generates positive number (msb = "0") operation generates negative number (msb = "1") .5 figure 4-1. register description format
s3c9644/c9648/p9648 control registers 4- 5 btcon ? basic timer control register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.4 watchdog timer enable bits 1 0 1 0 disable watchdog function any other value enable watchdog function .3 and .2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid setting .1 basic timer counter clear bit (note) 0 no effect 1 clear btcnt .0 basic timer divider clear bit (note) 0 no effect 1 clear both dividers note: when you write a "1" to btcon.0 (or btcon.1), the basic timer counter (or basic timer divider) is cleared. the bit is then cleared automatically to "0".
control registers s 3c9644/c9648/p9648 4- 6 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 oscillator irq wake-up function bit 0 enable irq for main system oscillator wake-up in power down mode 1 disable irq for main system oscillator wake-up in power down mode .6 and .5 not used for s3c9644/c9648/p9648 .4 and .3 cpu clock (system clock) selection bits (1) 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) (2) .2-.0 not used for s3c9644/c9648/p9648 notes: 1. after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4. 2. f osc means oscillator frequency.
s3c9644/c9648/p9648 control registers 4- 7 ep0csr ? control endpoint 0 status register f1h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 setup data end clear bit 0 no effect (when write) 1 to clear setup_end bit .6 out packet ready clear bit 0 no effect (when write) 1 to clear out_pkt_rdy bit .5 stall signal sending bit 0 no effect (when write) 1 to send stall signal .4 setup transfer end bit 0 no effect (when write) 1 sie sets this bit when a control transfer ends before data_end (bit3) is set .3 setup data end bit 0 no effect (when write) 1 mcu set this bit after loading or unloading the last packet data into the fifo .2 stall signal receive bit 0 mcu clear this bit to end the stall condition 1 sie sets this bit if a control transaction is ended due to a protocol violation .1 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit after writing a packet of data into endpoint0 fifo .0 out packet ready bit 0 no effect (when write) 1 sie sets this bit once a valid token is written to the fifo
control registers s 3c9644/c9648/p9648 4- 8 ep1csr ? control endpoint 1 status register f2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 data toggle sequence clear bit 0 no effect (when write) 1 mcu sets this bit to clear the data toggle sequence bit. the data toggle is initialized to data0. .6-.3 maximum packet size bits 0 no effect (when write) 1 these bits indicate the maximum packet size for in endpoint, and needs to be updated by the mcu before it sets in_pkt_rdy. once set, the contents are valid till mcu re-writes them. .2 fifo flush bit 0 no effect (when write) 1 when mcu writes a one to this register, the fifo is flushed, and in_pkt_rdy cleared. the mcu should wait for in_pkt_rdy to be cleared for the flush to take place. .1 force stall bit 0 no effect (when write) 1 mcu writes a 1 to this register to issue a stall handshake to usb. mcu clears this bit, to end the stall condition. .0 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit, after writing a packet of data into endpoint1 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit, so mcu can load the next packet.
s3c9644/c9648/p9648 control registers 4- 9 ep2csr ? control endpoint 2 status register f9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 data toggle sequence clear bit 0 no effect (when write) 1 mcu sets this bit to clear the data toggle sequence bit. the data toggle is initialized to data0. .6-.3 maximum packet size bits 0 no effect (when write) 1 these bits indicate the maximum packet size for in endpoint, and needs to be updated by the mcu before it sets in_pkt_rdy. once set, the contents are valid till mcu re-writes them. .2 fifo flush bit 0 no effect (when write) 1 when mcu writes a one to this register, the fifo is flushed, and in_pkt_rdy cleared. the mcu should wait for in_pkt_rdy to be cleared for the flush to take place. .1 force stall bit 0 no effect (when write) 1 mcu writes a 1 to this register to issue a stall handshake to usb. mcu clears this bit, to end the stall condition. .0 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit, after writing a packet of data into endpoint1 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit, so mcu can load the next packet.
control registers s 3c9644/c9648/p9648 4- 10 faddr ? usb function address register f0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w .7 not used for s3c9644/c9648/p9648 .6-.0 faddr this register holds the usb address assigned by the host computer. faddr is located at address f0h and is read/write addressable.
s3c9644/c9648/p9648 control registers 4- 11 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 ? ? ? ? read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 carry flag (c) 0 operation does not generate a carry or borrow condition .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or _ ?128 1 operation result is _ +127 or ?128 .3-0. not used for s3c9644/c9648/p9648
control registers s 3c9644/c9648/p9648 4- 12 p0conh ? port 0 control register (high byte) e6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0, p0.7 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 0, p0.6 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 port 0, p0.5 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .1 and .0 port 0, p0.4 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up
s3c9644/c9648/p9648 control registers 4- 13 p0conl ? port 0 control register (low byte) e7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0, p0.3 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 0, p0.2 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 port 0, p0.1 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .1 and .0 port 0, p0.0 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up
control registers s 3c9644/c9648/p9648 4- 14 p0int ? port 0 interrupt control register d8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p0.7 configuration bits 0 external interrupt disable 1 external interrupt enable .6 p0.6 configuration bits 0 external interrupt disable 1 external interrupt enable .5 p0.5 configuration bits 0 external interrupt disable 1 external interrupt enable .4 p0.4 configuration bits 0 external interrupt disable 1 external interrupt enable .3 p0.3 configuration bits 0 external interrupt disable 1 external interrupt enable .2 p0.2 configuration bits 0 external interrupt disable 1 external interrupt enable .1 p0.1 configuration bits 0 external interrupt disable 1 external interrupt enable .0 p0.0 configuration bits 0 external interrupt disable 1 external interrupt enable
s3c9644/c9648/p9648 control registers 4- 15 p0pnd ? port 0 interrupt pending register dah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write (note) r/w r/w r/w r/w r/w r/w r/w r/w .7 p0.7 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .6 p0.6 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .5 p0.5 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .4 p0.4 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .3 p0.3 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .2 p0.2 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .1 p0.1 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .0 p0.0 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write)
control registers s 3c9644/c9648/p9648 4- 16 p1conh ? port 1 control register (high byte) e8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 1, p1.7 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 1, p1.6 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 port 1, p1.5 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .1 and .0 port 1, p1.4 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up
s3c9644/c9648/p9648 control registers 4- 17 p1conl ? port 1 control register (low byte) e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 1, p1.3 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 1, p1.2 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 port 1, p1.1 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .1 and .0 port 1, p1.0 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up
control registers s 3c9644/c9648/p9648 4- 18 p2conh ? port 2 control register (high byte) eah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 2, p2.7 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 2, p2.6 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 port 2, p2.5 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .1 and .0 port 2, p2.4 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up
s3c9644/c9648/p9648 control registers 4- 19 p2conl ? port 2 control register (low byte) ebh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 2, p2.3 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 2, p2.2 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 port 2, p2.1 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .1 and .0 port 2, p2.0 configuration bits 0 0 schmitt trigger input, rising edge external interrupt 0 1 schmitt trigger input, falling edges external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up
control registers s 3c9644/c9648/p9648 4- 20 p2int ? port 2 interrupt enable register ech bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p2.7 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .6 p2.6 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .5 p2.5 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .4 p2.4 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .3 p2.3 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .2 p2.2 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .1 p2.1 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .0 p2.0 interrupt enable bit 0 external interrupt disable 1 external interrupt enable
s3c9644/c9648/p9648 control registers 4- 21 p2pnd ? port 2 interrupt pending register edh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write (note) r/w r/w r/w r/w r/w r/w r/w r/w .7 p2.7 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .6 p2.6 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .5 p2.5 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .4 p2.4 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .3 p2.3 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .2 p2.2 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .1 p2.1 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) .0 p2.0 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write) note: to clear a port 2 interrupt pending condition, write a "0" to the corresponding p2pnd register bit location.
control registers s 3c9644/c9648/p9648 4- 22 p3con ? port 3 control register e5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 3, p3.3 configuration bits 0 0 schmitt trigger input 0 1 system clock output(clo) mode. clo comes from system clock circuit. 1 0 push-pull output 1 1 n-channel open-drain output mode .5 and .4 port 3, p3.2 configuration bits 0 x schmitt trigger input 1 0 push-pull output 1 1 n-channel open-drain output mode .3 and .2 port 3, p3.1 configuration bits 0 x schmitt trigger input 1 0 push-pull output 1 1 n-channel open-drain output mode .1 and .0 port 3, p3.0 configuration bits 0 x schmitt trigger input 1 0 push-pull output 1 1 n-channel open-drain output mode note: "x" means don't care
s3c9644/c9648/p9648 control registers 4- 23 p4con ? port 4 control register eeh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 4, p4.3 configuration control bits 0 0 schmitt trigger input, falling edge external interrupt with pull-up 0 1 n-ch open drain output mode with pull-up 1 0 n-ch open drain output mode 1 1 output pull-pull mode .5 and .4 port 4, p4.2 configuration control bits 0 0 schmitt trigger input, falling edge external interrupt with pull-up 0 1 n-ch open drain output mode with pull-up 1 0 n-ch open drain output mode 1 1 output pull-pull mode .3 and .2 port 4, p4.1 configuration control bits 0 0 schmitt trigger input, falling edge external interrupt with pull-up 0 1 n-ch open drain output mode with pull-up 1 0 n-ch open drain output mode 1 1 output pull-pull mode .1 and .0 port 4, p4.0 configuration control bits 0 0 schmitt trigger input, falling edge external interrupt with pull-up 0 1 n-ch open drain output mode with pull-up 1 0 n-ch open drain output mode 1 1 output pull-pull mode
control registers s 3c9644/c9648/p9648 4- 24 p4intpnd ? port 4 interrupt enable and pending register efh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p4.3 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .6 p4.2 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .5 p4.1 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .4 p4.0 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .3 p4.3 interrupt pending bit 0 no pending (when bit is read)/clear pending bit (when bit is write) 1 pending (when bit is read)/no effect (when bit is write) .2 p4.2 interrupt pending bit 0 no pending (when bit is read)/clear pending bit (when bit is write) 1 pending (when bit is read)/no effect (when bit is write) .1 p4.1 interrupt pending bit 0 no pending (when bit is read)/clear pending bit (when bit is write) 1 pending (when bit is read)/no effect (when bit is write) .0 p4.0 interrupt pending bit 0 no pending (when bit is read)/clear pending bit (when bit is write) 1 pending (when bit is read)/no effect (when bit is write)
s3c9644/c9648/p9648 control registers 4- 25 ps2conint ? ps2 control and interrupt pending register (ps2 mode only) eeh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 d+/ps2 configuration control bits 0 0 schmitt trigger input, falling edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 d-/ps2 configuration control bits 0 0 schmitt trigger input, falling edge external interrupt 0 1 schmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .4 d+/ps2 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .3 d-/ps2 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .1 d+/ps2 interrupt pending bit 0 no pending (when bit is read)/clear pending bit (when bit is write) 1 pending (when bit is read)/no effect (when bit is write) .0 d-/ps2 interrupt pending bit 0 no pending (when bit is read)/clear pending bit (when bit is write) 1 pending (when bit is read)/no effect (when bit is write)
control registers s 3c9644/c9648/p9648 4- 26 pwrmgr ? usb power management register f8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.2 not used for s3c9644/c9648/p9648 .1 resume signal sending bit 0 resume signal is ended 1 while in suspend state, if the mcu wants to initiate a resume, it writes a 1 to this register for 10ms (maximum of 15ms), and clears this register. in suspend mode if this bit is a 1, usb generates resume signaling. .0 suspend status bit 0 cleared when mcu writes a zero to resume signal sending bit or function receives resume signal from the host while in suspend mode 1 this bit is set when suspend interrupt occur
s3c9644/c9648/p9648 control registers 4- 27 sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w .7-.3 not used for s3c9644/c9648/p9648 .2 global interrupt enable bit (note) 0 disable global interrupt processing 1 enable global interrupt processing .1 and .0 page selection bits 0 0 addressing page 0 locations for s3c9644/c9648/p9648 other values enable global interrupt processing note : sym must be selected bit 1 and 0 into 00 for s3c9644/c9648/p9648.
control registers s 3c9644/c9648/p9648 4- 28 t0con ? timer 0 control register d2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 t0 counter input clock selection bits 0 0 cpu clock/4096 0 1 cpu clock/256 1 0 cpu clock/8 1 1 invalid selection .5 and .4 t0 operating mode selection bits 0 0 interval timer mode (the counter is automatically cleared whenever t0data value equals to t0cnt value) 0 1 invalid selection 1 0 1 1 overflow mode (ovf interrupt can occur) .3 t0 counter clear bit (t0clr) 0 no effect when written 1 clear t0 counter .2 t0 overflow interrupt enable bit (t0ovf) 0 disable t0 overflow interrupt 1 enable t0 overflow interrupt .1 t0 match interrupt enable bit (t0int) 0 disable t0 match interrupt 1 enable t0 match interrupt .0 t0 interrupt pending bit (t0pnd) 0 no interrupt pending/ clear this pending bit (when write) 1 interrupt is pending(when read)/no effect(when write) note: when you write a "1" to t0con.3, the timer 0 counter is cleared. the bit is then cleared automatically to "0".
s3c9644/c9648/p9648 control registers 4- 29 usbpnd ? usb interrupt pending register f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.4 not used for s3c9644/c9648/p9648 .3 endpoint 2 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when endpoint2 needs to be serviced .3 resume interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 while in suspend mode, if resume signaling is received this bit gets set .2 suspend interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when suspend signaling is received .1 endpoint1 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when endpoint1 needs to be serviced .0 endpoint0 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, while endpoint 0 needs to serviced. it is set under the following conditions; ? out_pkt_rdy is set ? in_pkt_rdy get cleared ? sent_stall gets set ? data_end gets cleared ? setup_end gets set
control registers s 3c9644/c9648/p9648 4- 30 usbint ? usb interrupt enable register f7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 1 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.3 not used for s3c9644/c9648/p9648 .3 endpoint2 interrupt pending bit 0 disable endpoint 2 interrupt 1 enable endpoint 2 interrupt .2 suspend/resume interrupt enable bit 0 disable suspend and reseme interrupt 1 enable suspend and reseme interrupt .1 endpoint1 interrupt pending bit 0 disable endpoint 1 interrupt 1 enable endpoint 1 interrupt .0 endpoint0 interrupt pending bit 0 disable endpoint 0 interrupt 1 enable endpoint 0 interrupt
s3c9644/c9648/p9648 control registers 4- 31 usbsel ? usb/ps2 mode select register fbh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? ? ? ? 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.1 not used for s3c9644/c9648/p9648 .0 usb/ps2 mode select bit 0 ps2 mode 1 usb mode
control registers s 3c9644/c9648/p9648 4- 32 xcon ? usb signal crossover point control register feh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7-.6 not used for s3c9644/c9648/p9648 .5-.0 usb signal crossover point control bit edge delay control bit 5, (2) bit 4, (1) bit 3, (0) delay value delay unit 0 0 0 rise 0 0 1 1 edge 1 0 2 (about) 1 1 4 2.5nsec 0 0 0 fall 1 0 1 1 edge 1 0 2 1 1 4
s3c9644/c9648/p9648 control registers 4- 33 usbrst ? usb reset register ffh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? ? ? ? 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.1 not used for s3c9644/c9648/p9648 .0 usb reset signal receive bit 0 clear reset signal bit 1 this bit is set when host send usb reset signal
s3c9644/c9648/p9648 interrupt structure 5- 1 5 interrupt structure overview the sam87ri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a interrupt vector which is assigned in rom address 0000h-0001h. vector sources 0000h 0001h s1 s2 s3 sn notes: 1. the sam87ri interrupt has only one vector address (0000h-0001h) 2. the number of sn value is expandable. figure 5-1. s3c9-series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. the system-level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source enable and disable settings in the c orresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.2 is the enable and disable bit for global interrupt processing respectively, by modifying sym.2. an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. although you can manipulate sym.2 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s3c9644/c9648/p9648 5- 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87ri, the order of service is determined by a sequence of source which is executed in interrupt service routine. s q r "ei" instruction execution reset source interrupts vector interrupt cycle global interrupt control (ei, di instructions) interrupt pending register source interrupt enable interrupt priority is determined by software polling method figure 5-2. interrupt function diagram
s3c9644/c9648/p9648 interrupt structure 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt acknowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be enabled (ei, sym.2 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym.2 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.2 to "1"(ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9644/c9648/p9648 5- 4 s3c9644/c9648/p9648 interrupt structure the s3c9644/c9648/p9648 microcontroller has fourteen peripheral interrupt sources: ? timer 0 match interrupt ? timer 0 overflow interrupt ? eight external interrupts for port 2, p2. 0-p2.7 ? four external interrupts for port 4, p4.0-p4.3 vector sources timer 0 match interrupt timer 0 overflow interrupt p0.x external interrupt p2.x external interrupt pending bits 0000h enable/disable t0con.0 ei/di (sym.2) t0con.1 t0con.2 p0pnd.x p0int.x p2pnd.x p2int.x p4intpnd.0-3 p4intpnd.4-7 p4intpnd.0 usbint.0 p4intpnd.1 p4intpnd.4 ps2inpnd.0 ps2intpnd.2 p4.0-3external interrupt endpoint 0 interrupt endpoint 1 interrupt endpoint 2 interrupt d-/ps2 interrupt d+/ps2 interrupt suspend interrupt resume interrupt note: ?x? means 0 -7 bit. ps2int pnd.1 usbpnd.2 usbpnd.3 usbint.2 usbint.2 usbint.1 usbint.3 ps2intpnd.3 figure 5-3. s3c9644/c9648/p9648 interrupt structure
s3c9644/c9648/p9648 clock circuit 7- 1 7 clock circuit s3c9644 s3c9648 c1 c2 x in x out 6 mhz figure 7-1. main oscillator circuit (crystal/ceramic oscillator) main oscillator logic to increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. for this reason, very high resolution waveforms (square signal edges) must be generated in order for the cpu to efficiently process logic operations. clock status during power-down modes the two power-down modes, stop mode and idle mode, affect clock oscillation as follows: ? in stop mode, the main oscillator "freezes", halting the cpu and peripherals. the contents of the register file and current system register values are retained. stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with rc-delay noise filter (for s3c9644/c9648/p9648, int0-int2). ? in idle mode, the internal clock signal is gated off to the cpu, but not to interrupt control and the timer. the current cpu status is preserved, including stack pointer, program counter, and flags. data in the register file is retained. idle mode is released by a reset or by an interrupt (external or internally-generated).
clock circuit s3c96 44/c9648/p9648 7- 2 system clock control register (clkcon) the system clock control register, clkcon, is located in location d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable (clkcon.7) ? oscillator frequency divide-by value: non-divided, 2, 8 or 16 (clkcon.4 and clkcon.3) the clkcon register controls whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function). the irq wake-up enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2 or f osc /8. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 system clock control register (clkcon) d4h, r/w not used for s3c9644/c9648/p9648 divide-by selection bits for cpu clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc (non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function 1 = disable irq for main system oscillator wake-up function not used for s3c9644/c9648/p9648 figure 7-2. system clock control register (clkcon)
s3c9644/c9648/p9648 clock circuit 7- 3 stop instruction noise filter main osc clkcon.7 int pin oscillator wake-up 1/2 1/8 1/16 m u x clkcon.3, .4 cpu clock p3con p3.3/clo oscillator stop figure 7-3. system clock circuit diagram
s3c9644/c9648/p9648 reset and power-dow n 8- 1 8 reset and power-down system reset overview during a power-on reset, the voltage at v dd is high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this brings the s3c9644/c9648/p9648 into a known operating status. the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimum required oscillation stabilization time for a reset is approximately 10ms (@ 2 16 / f osc , f osc = 6 mhz). when a reset occurs during normal operation (with both v dd and reset at high level), the signal at the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then set to their default hardware reset values (see table 8-1). the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0-4 are set to schmitt trigger input mode and all pull-up resistors are disabled. ? peripheral control and data registers are disabled and reset to thei r initial values. ? the program counter is loaded with the rom reset address, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the address stored in rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
reset and power-down s3c9644/c9648/p964 8 8- 2 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 300 a. all system functions are halted when the clock "freezes", but data stored in the internal regi ster file is retained. stop mode can be released in one of two ways: by a reset signal or by an external interrupt. using reset to release stop mode stop mode is released when the reset signal is released and returns to high level. all system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the oscillation stabilization interval has elapsed, the cpu executes the system initialization routine by fetching the 16-bit address stored in rom locations 0100h and 0101h. using an external interrupt to release stop mode only external interrupts with an rc-delay noise filter circuit can be used to release stop mode (clock-related external interrupts cannot be used). external interrupts int0-int2 in the s3c9644/c9648/p9648 interrupt structure meet this criteria. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while select peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu, but not to interrupt logic and timer/counters. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interr upt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. following the iret from the service routine, the instruction immediately following the one that initiated idle mode is executed. note only external interrupts that are not clock-related can be used to release stop mode. to release idle mode, however, any type of interrupt (that is, internal or external) can be used.
s3c9644/c9648/p9648 reset and power-dow n 8- 3 hardware reset values tables 8-1 through 8-3 list the values for cpu and system registers, peripheral control registers and peripheral data registers following a reset operation in normal operating mode. the following notation is used in these tables to represent specific reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined following a reset. ? a das h ('-') means that the bit is either not used or not mapped. table 8-1. register values after a reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 general purpose registers ? 000-191 00h-bfh x x x x x x x x working registers r0 - r15 192-207 c0h-cfh x x x x x x x x timer 0 counter t0cnt 208 d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data 209 d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con 210 d2h 0 0 0 0 0 0 0 0 location d3h is not mapped. clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h 0 0 0 0 ? ? ? ? locations d6h - d8h are not mapped. port 0 interrupt control register p0int 216 d8h 0 0 0 0 0 0 0 0 stack pointer sp 217 d9h x x x x x x x x port 0 interrupt pending register p0pnd 218 dah 0 0 0 0 0 0 0 0 location dbh is not mapped. basic timer control register btcon 220 dch 0 0 0 0 0 0 0 0 basic timer counter btcnt 221 ddh 0 0 0 0 0 0 0 0 location deh is not mapped. system mode register sym 223 dfh 0 ? ? ? ? 0 0 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 port 4 data register p4 228 e4h 0 0 0 0 0 0 0 0
reset and power-down s3c9644/c9648/p964 8 8- 4 table 8-1. register values after a reset (continued) bank 0 register name mnemonic address bit values after a reset dec hex 7 6 5 4 3 2 1 0 port 3 control register p3con 229 e5h 0 0 0 0 0 0 0 0 port 0 control register (high byte) p0conh 230 e6h 0 0 0 0 0 0 0 0 port 0 control register (low byte) p0conl 231 e7h 0 0 0 0 0 0 0 0 port 1 control register (high byte) p1conh 232 e8h 0 0 0 0 0 0 0 0 port 1 control register (low byte) p1conl 233 e9h 0 0 0 0 0 0 0 0 port 2 control register (high byte) p2conh 234 eah 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl 235 ebh 0 0 0 0 0 0 0 0 port 2 interrupt enable register p2int 236 ech 0 0 0 0 0 0 0 0 port 2 interrupt pending register p2pnd 237 edh 0 0 0 0 0 0 0 0 port 4 control register p4con 238 eeh 0 0 0 0 0 0 0 0 port 4 interrupt enable/pending register p4intpnd 239 efh 0 0 0 0 0 0 0 0 usb function address register faddr 240 f0h 0 0 0 0 0 0 0 0 control endpoint status register ep0csr 241 f1h 0 0 0 0 0 0 0 0 interrupt endpoint status register ep1csr 242 f2h 0 0 0 0 0 0 0 0 control endpoint byte count register ep0bcnt 243 f3h 0 0 0 0 0 0 0 0 control endpoint fifo register ep0fifo 244 f4h x x x x x x x x interrupt endpoint fifo register ep1fifo 245 f5h x x x x x x x x usb interrupt pending register usbpnd 246 f6h 0 0 0 0 0 0 0 0 usb interrupt enable register usbint 247 f7h 0 0 0 0 0 0 1 1 usb power management register pwrmgr 248 f8h 0 0 0 0 0 0 0 0 interrupt endpoint 2 control status register ep2csr 249 f9h 0 0 0 0 0 0 0 0 interrupt endpoint 2 fifo register ep2fifo 250 fah x x x x x x x x usb/ps2 mode select register usbsel 251 fbh 0 0 0 0 0 0 0 0 d+/ps2, d-/ps2 data register (only ps2 mode) ps2data 252 fch 0 0 0 0 0 0 0 0 ps2 control and interrupt pending register ps2conint 253 fdh 0 0 0 0 0 0 0 0 usb tranceiver crossover point control register xcon 254 feh ? ? 0 0 0 0 0 0 usb reset register usbrst 255 ffh x x x x x x x 1
s3c9644/c9648/p9648 i/o ports 9- 1 9 i/o ports overview the s3c9644/c9648/p9648 usb mode has five i/o ports (0-4) with a total of 32 pins. ps2 mode has six i/o ports (0-4 and d+/ps2, d-/ps2) with a total of 34 pins. you can access these ports directly by writing or reading port data register addresses. for keyboard applications, ports 0, 1 and 2 are usually configured as keyboard matrix input/output. port 3 can be configured as led drive. port 4 is used for host communication or for controlling a mouse or other external device. table 9-1. s3c9644/c9648/p9648 port configuration overview port function description programmability 0 bit-programmable i/o port for schmitt trigger input or open-drain output. port0 can be individually configured as external interrupt inputs. pull-up resistors are assignable by software. bit 1 bit-programmable i/o port for schmitt trigger input or open-drain output. pull-up resistors are assignable by software. bit 2 bit-programmable i/o port for schmitt trigger input or open-drain output. port2 can be individually configured as external interrupt inputs. pull-up resistors are assignable by software. bit 3 bit-programmable i/o port for schmitt trigger input, open-drain or push- pull output. p3.3 can be used to system clock output (clo) pin. bit 4 bit-programmable i/o port for schmitt trigger input or open-drain output or push-pull output. port4 can be individually configured as external interrupt inputs. in output mode, pull-up resistors are assignable by software. but in input mode, pull-up resistors are fixed. bit d+/ps2 d-/ps2 (ps2 mode only) bit-programmable i/o port for schmitt trigger input or open-drain output or push-pull output. this port individually configured as external interrupt inputs. in output mode, pull-up resistors are assignable by software. but in input mode, pull-up resistors are fixed. bit
i/o ports s3c9644/c 9648/p9648 9- 2 port data registers table 9-2 gives you an overview of the port data register names, locations and addressing characteristics. data registers for ports 0-4 have the structure shown in figure 9-1. table 9-2. port data register summary register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 4 data register p4 228 e4h r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 i/o port n data register (n = 0?4) pn.7 pn.6 pn.5 pn.4 pn.3 pn.2 pn.1 pn.0 note : because only the four lower-nibble pins of port 3 and port 4 are mapped, data register bits p3.4-p3.7 and p4.4-p4.7 are not used. figure 9-1. port data register format
s3c9644/c9648/p9648 i/o ports 9- 3 port 0 and port 1 ports 0 bit-programmable, general-purpose, i/o ports. you can select schmitt trigger input mode, n-ch open drain output mode. you can access ports 0 and 1 directly by writing or reading the corresponding port data registers ? p0 (e0h) and p1 (e1h). a reset clears the port control registers p0conh, p0conl, p1conh and p1conl to '00h', configuring all port 0 and port 1 pins as schmitt trigger inputs. in typical keyboard controller applications, the sixteen port 0 and port 1 pins can be used to check pressed key from keyboard matrix by generating keystrobe output signals. 7,5,3,1 0 0 1 1 6,4,2,0 0 1 0 1 port mode selection schmitt trigger input, rising edge external interrupt mode schmitt trigger input, falling edge external interrupt mode with pull-up n-ch open drain output mode n-ch open drain output mode with pull-up msb lsb .7 .6 .5 .4 .3 .2 .1 .0 port 0 control registers p0conh, e6h, r/w, p0conl, e7h, r/w p0.7/int2 p0.6/int2 p0.5/int2 p0.4/int2 p0.3/int2 p0.2/int2 p0.1/int2 p0.0/int2 p0conh p0conl figure 9-2. port 0 control registers (p0conh, p0conl)
i/o ports s3c9644/c 9648/p9648 9- 4 7,5,3,1 0 0 1 1 6,4,2,0 0 1 0 1 port mode selection schmitt trigger input mode schmitt trigger input mode with pull-up n-ch open drain output mode n-ch open drain output mode with pull-up msb lsb .7 .6 .5 .4 .3 .2 .1 .0 port 1 control registers p1conh, e8h, r/w, p1conl, e9h, r/w p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p1conh p1conl figure 9-3. port 1 control registers (p1conh, p1conl)
s3c9644/c9648/p9648 i/o ports 9- 5 port 2 port 2 is an 8-bit i/o port with individually configurable pins. it can be used for general i/o (schmitt trigger input mode or push-pull output mode). or, you can use port 2 pins as external interrupt (int0) inputs. in addition, you can configure a pull-up resistor to individual pins using control register settings. all port 2 pin circuits have noise filters. in typical keyboard controller applications, the port 2 pins are programmed to receive key input data from the keyboard matrix. you can address port 2 bits directly by writing or reading the port 2 data register, p2 (e2h). the port 2 high-byte and low-byte control registers, p2conh and p2conl, are located at addresses eah and ebh, respectively. two additional registers, are used for interrupt control: p2int (ech) and p2pnd (edh). by setting bits in the port 2 interrupt enable register p2int, you can configure specific port 2 pins to generate interrupt requests when rising or falling signal edges are detected. the application program polls the port 2 interrupt pending register, p2pnd, to detect interrupt requests. when an interrupt request is acknowledged, the corresponding pending bit must be cleared by the interrupt service routine. in case of keyboard applications, the port 2 pins can be used to read key value from key matrix. 7,5,3,1 0 0 1 1 6,4,2,0 0 1 0 1 port mode selection schmitt trigger input, rising edge external interrupt schmitt trigger input, falling edge external interrupt with pull-up n-ch open drain n-ch open drain with pull-up msb lsb .7 .6 .5 .4 .3 .2 .1 .0 port 2 control registers p2conh, eah, r/w, p2conl, ebh, r/w p2.7/int0 p2.6/int0 p2.5/int0 p2.4/int0 p2.3/int0 p2.2/int0 p2.1/int0 p2.0/int0 p2conh p2conl figure 9-4. port 2 control registers (p2conh, p2conl)
i/o ports s3c9644/c 9648/p9648 9- 6 port 2 interrupt enable register (p2int) ech, r/w port 2 interrupt control settings: 0 = disable interrupt at p2.n pin 1 = enable interrupt at p2.n pin msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p2.7/int0 p2.6/int0 p2.5/int0 p2.4/int0 p2.3/int0 p2.2/int0 p2.1/int0 p2.0/ int0 figure 9-5. port 2 interrupt enable register (p2int) port 2 interrupt pending register (p2pnd) edh, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p2.7/int0 p2.6/int0 p2.5/int0 p2.4/int0 p2.3/int0 p2.2/int0 p2.1/int0 p2.0/int0 port 2 interrupt request pending bits: 0 = no interrupt is pending 1 = interrupt request is pending figure 9-6. port 2 interrupt pending register (p2pnd)
s3c9644/c9648/p9648 i/o ports 9- 7 port 3 port 3 is a 4-bit, bit-configurable, general i/o port. it is designed for high-current functions such as led drive. a reset configures p3.0-p3.3 to schmitt trigger input mode. using the p3con register (e5h), you can alternatively configure the port 3 pins as n-channel, open-drain outputs. p3.3 can be used to system clock output (clo) port. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 port3 control register (p3con) e5h, r/w 5,3,1 0 1 1 4,2,0 x 0 1 port mode selection (pin 3.2-pin 3.0) schmitt trigger input push-pull output n-ch open drain output p3.3/clo p3.2 p3.1 p3.0 7 0 0 1 1 6 0 1 0 1 port mode selection (pin 3.3) schmitt trigger input system clock output (clo) mode. clo comes from system clock circuit. push-pull output n-ch open drain output figure 9-7. port 3 control register (p3con)
i/o ports s3c9644/c 9648/p9648 9- 8 port 4 port 4 is a 4-bit i/o port with individually configurable pins. it can be used for general i/o (schmitt trigger, n-ch open drain output mode, push-pull output mode). or, you can use port 4 pins as external interrupt (int1) inputs. in addition, you can configure a pull-up resistor to individual pins using control register settings. all port 4 pins have noise filters. a reset configures p4.0-p4.3 to input mode. you address port 4 directly by writing or reading the port 4 data register, p4 (e4h). the port 4 control register, p4con, is located at eeh. a additional registers used for interrupt control: p4intpnd (efh). by setting bits in the port 4 interrupt enable and pending register p4intpnd.7-p4intpnd.4, you can configure specific port 4 pins to generate interrupt requests when falling signal edges are detected. the application program polls the interrupt pending register, p4intpnd.3-p4intpnd.0, to detect interrupt requests. when an interrupt request is acknowledged, the corresponding pending bit must be cleared by the interrupt service routine. port 4 control register (p4con) eeh, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p4.3/int1 p4.2/int1 p4.1/int1 p4.0/int1 p4con pin configuration settings: 00 01 10 11 schmitt trigger input, falling edge external interrupt with pull-up n-ch open drain output with pull-up register n-ch open drain output push-pull output figure 9-8. port 4 control register (p4con)
s3c9644/c9648/p9648 i/o ports 9- 9 port 4 interrupt enable and pending register (p4intpnd) efh, r/w p4intpnd.7 - 4 : port 4 interrupt control settings: 0 = disable interrupt at p4.n pin 1 = enable interrupt at p4.n pin p4intpnd.3 - 0 : port 4 interrupt pending bits: 0 = no interrupt request pending 1 = interrupt request is pending msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p4.3/int1 p4.2/int1 p4.1/int1 p4.0/int1 p4.3/int1 p4.2/int1 p4.1/int1 p4.0/int1 figure 9-9. port 4 interrupt enable and pending register (p4intpnd)
i/o ports s3c9644/c 9648/p9648 9- 10 d+/ps2, d-/ps2 ps2 control and interrupt and pending register fdh, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 d+ /ps2 d- /ps2 ps2conint.3-2: interrupt control setting 0 = disable interrupt 1 = enable interrupt ps2conint.7-4 pin configuration settings: d+/ps2, d-/ps2 00 01 10 11 schmitt trigger input, falling edge external interrupt schmitt trigger input, falling edge external interrupt with pull-up n-ch open drain output n-ch open drain output with pull-up register ps2conint.3 - 2: interrupt control setting 0 = no interrupt request pending 1 = interrupt request is pending d+ /ps2int d+ /ps2pnd d- /ps2int d- /ps2pnd note : use only ps2mode figure 9-10. ps2conint register (ps2conint)
s3c9644/c9648/p9648 basic time r and timer 0 10- 1 10 basic timer and timer 0 module overview the s3c9644/c9648/p9648 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. the 8 -bit timer/counter is called timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 4096, 1024, or 128) with multiplexer ? 8-bit basic timer counter, btcnt (ddh, read-only) ? ba sic timer control register, btcon (dch, read/write) timer 0 timer 0 has two operating modes, one of which you select by the appropriate t0con setting: ? interval timer mode ? overflow mode timer 0 has the following functional components: ? clock frequency divider (f osc divided by 4096, 256, or 8) with multiplexer ? 8-bit counter (t0cnt), 8-bit comparator, and 8-bit reference data register (t0data) ? timer 0 overflow interrupt (t0ovf) and match interrupt (t0int) generation ? timer 0 con trol register, t0con
basic timer and timer 0 s3c9644/c9648/p 9648 10- 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. a reset clears btcon to '00h'. this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code '1010b' to the basic timer register control bits btcon.7-btcon.4. the 8-bit basic timer counter, btcnt, can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to btcon.0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 basic timer control register (btcon) dch, r/w watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 = f osc /4096 01 = f osc /1024 10 = f osc /128 11 = invalid selection figure 10-1. basic timer control register (btcon)
s3c9644/c9648/p9648 basic time r and timer 0 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal to generate a reset by setting btcon.7-btcon.4 to any value other than '1010b' (the '1010b' value disables the watchdog function). a reset clears btcon to '00h', automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting) divided by 4096 as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset o ccurred, the basic timer counter will increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set. 4. when a btcnt.4 is set, normal cpu operation resumes. figures 10-2 and 10-3 shows the oscillation stabilization time on reset and stop mode release
basic timer and timer 0 s3c9644/c9648/p 9648 10- 4 v dd reset internal reset release oscillator (xout) btcnt clock btcnt value t wait=(4096x16)/fosc basic timer increment and cpu operations are idle mode oscillation stabilization time normal operating mode 00000b 10000b 0.5 v dd reset release voltage trst ? rc oscillator stabilization time 0.5 v dd note: duration of the oscillator stabilization wait time, twait, when it is released by a power-on-reset is 4096x16/fosc. trst ? rc (r is external resister and c is on chip capacitor) figure 10-2. oscillation stabilization time on reset
s3c9644/c9648/p9648 basic time r and timer 0 10- 5 v dd external interrupt reset stop release signal oscillator (xout) btcnt clock btcnt value t wait basic timer increment stop mode release signal stop instruction execution normal operating mode stop mode oscillation stabilization time normal operating mode 00000b 10000b t wait (when fosc is 6 mhz) t wait btcon.3 btcon.2 10.92 ms (4096 x 16) / fosc 0 0 2.7 ms 0 1 0.34 ms 1 0 1 1 (1024 x 16) / fosc (128 x 16) / fosc invalid setting ? note: duration of the oscillator stabilization wait time, twait, it is released by an interrupt is determined by the setting in basic timer control register, btcon. figure 10-3. oscillation stabilization time on stop mode release
basic timer and timer 0 s3c9644/c9648/p 9648 10- 6 timer 0 control register (t0con) t0con is located at address d2h, and is read/write addressable. a reset clears t0con to '00h'. this sets timer 0 to normal interval match mode, selects an input clock frequency of f osc /4096, and disables the timer 0 overflow interrupt and match interrupt. you can clear the timer 0 counter at any time during normal operation by writing a "1" to t0con.3. the timer 0 overflow interrupt can be enabled by writing a "1" to t0con.2. when a timer 0 overflow interrupt occurs and is serviced by the cpu, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. to enable the timer 0 match interrupt, you must write t0con.1 to "1". to detect an interrupt pending condition, the application program polls t0con.0. when a "1" is detected, a timer 0 match/ capture interrupt is pending. when the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 timer 0 control register (t0con) d2h, r/w timer 0 interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending (when read) no effect (when write) timer 0 match interrupt enable bit: 0 = disable match interrupt 1 = enable match interrupt timer 0 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 input clock selection bits: 00 = f osc /4096 01 = f osc /256 10 = f osc /8 11 = invalid selection timer 0 operating mode selection bits: 00 = interval match mode 01 = invalid selection 10 = invalid selection 11 = overflow mode figure 10-4. timer 0 control register (t0con)
s3c9644/c9648/p9648 basic time r and timer 0 10- 7 timer 0 function description interval match mode in interval match mode, a match signal is generated when the counter value is identical to the value written to the t0 reference data register, t0data. the match signal generates a timer 0 match interrupt and then clears the counter. if for example, you write the value '10h' to t0data, the counter will increment until it reaches '10h'. at this point, the t0 match interrupt is generated, the counter value is reset and counting resumes. overflow mode in overflow mode, a overflow signal is generated regardless of the value written to the t0 reference data register when the counter value is overflowed. the overflow signal generates a timer 0 overflow interrupt and then t0 counter is cleared. counter comparator t0data buffer register clk r match t0int t0ovf data bus 8 t0pnd t0data when 8-bit counter is cleared, this buffer is open data bus 8 figure 10-5. simplified timer 0 function diagram: interval timer mode
basic timer and timer 0 s3c9644/c9648/p 9648 10- 8 data bus data bus div r bit 0 r div xin 1/4096 1/1024 1/128 1/8 bits 7, 6, 5, 4 reset 8-bit counter ( t0cnt , read-only) 8-bit comparator r bits 5, 4 match signal bit 3 t0clr irq basic timer control register timer 0 control register bits 7, 6 bit 1 reset or stop 8-bit basic counter ( btcnt , read-only) bit 2 ovint t0data buffer register ovf 1/128 mux 2-bit sca ler data bus bits 3, 2 8 write '1010xxxxb' to disable. overflow 8 8 8 t0data 8 when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. match/ overflow bit 1 t0int bit 0 when 8-bit counter is cleared this open.l figure 10-6. basic timer and timer 0 block diagram
s3c9644/c9648/p9648 universal serial bu s 11- 1 11 universal serial b us overview universal serial bus (usb) is a communication architecture that supports data transfer between a host computer and a wide range of pc peripherals. usb is actually a cable bus in which the peripherals share its bandwidth through a host scheduled token based protocol. the usb module in s3c9644/c9648/p9648 is designed to serve at a low speed transfer rate (1.5 mbs) usb device as described in the universal serial bus specification revision 1.0. s3c9644/c9648/p9648 can be briefly describe as a microcontroller with sam 87ri core with an on-chip usb peripheral as can be seen in figure 11-1. the s3c9644/c9648/p9648 comes equipped with serial interface engine (sie), which handles the communication protocol of the usb. the s3c9644/c9648/p9648 supports the following control logic: packet decoding/generation, crc generation/checking, nrzi encoding/decoding, sync detection, eop (end of packet) detection and bit stuffing. s3c9644/c9648/p9648 supports two types of data transfers; control and interrupt. three endpoints are used in this device; endpoint 0, endpoint 1, and endpoint 2 . please refer to the usb specification revision 1.0 for detail description of usb.
universal serial bus s3c9644/c9648/p964 8 11- 2 transceiver sie (serial interface engine) endpoint0 fifo endpoint1,2 fifo sam87ri core d-/ps2 d +/ps2 data bus voltage regulator figure 11-1. usb peripheral interface
s3c9644/c9648/p9648 universal serial bu s 11- 3 serial bus interface engine (sie) the serial interface engine interfaces to the usb serial data and handles, deserialization/serialization of data, nrzi encoding/decoding, clock extraction, crc generation and checking, bit stuffing and other specifications pertaining to the usb protocol such as handling inter packet time out and pid decoding. control logic the usb control logic manages data movements between the cpu and the transceiver by manipulating the transceiver and the endpoint register. this includes both transmit and receive operations on the usb. the logic contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use this to determine the number of bytes to transfer. the same buffer is used for receive transactions to count the number of bytes received and transfer that number to the receive endpoint's byte count register at the end of the transaction. the control logic in s3c9644/c9648/p9648, when transmitting, manages parallel to serial conversion, packet generation, crc generation, nrzi encoding and bit stuffing. when receiving, the control logic in s3c9644/c9648/p9648 handles sync detection, packet decoding, eop (end of packet) detection, bit stuffing, nrzi decoding, crc checking and serial to parallel conversion bus protocol all bus transactions involve the transmission of packets. s3c9644/c9648/p9648 supports three packet types; token, data and handshake. each transaction starts when the host controller sends a token packet to the usb device. the token packets are generated by the usb host and decoded by the usb device. a token packet includes the type description, direction of the transaction, usb device address and the endpoint number. data and handshake packets are both decoded and generated by the usb device. in any transaction, the data is transferred from the host to a device or from a device to the host. the transaction source then sends a data packet or indicates that it has no data to transfer. the destination then responds with a handshake packet indicating whether the transfer was successful. data transfer types usb data transfer occurs between the host software and a specific endpoint on the usb device. an endpoint supports a specific type of data transfer. the s3c9644/c9648/p9648 supports two data transfer endpoints: control and interrupt. control transfer configures and assigns an address to the device when detected. control transfer also supports status transaction, returning status information from device to host. interrupt transfer refers to a small, spontaneous data transfer from usb device to host. endpoints communication flows between the host software and the endpoints on the usb device. each endpoint on a device has an identifier number. in addition to the endpoint number, each endpoint supports a specific transfer type. s3c9644/c9648/p9648 supports three endpoints: endpoint 0 supports control transfer, and endpoint 1 and endpoint 2 supports interrupt transfer.
universal serial bus s3c9644/c9648/p964 8 11- 4 usb function address register (faddr) this register holds the usb address assigned by the host computer. faddr is located at address f0h and is read/write addressable. bit7 not used bit6-0 faddr: mcu updates this register once it decodes a set_address command. mcu must write this register before it clears out_pkt_rdy (bit0) and sets data_end (bit3) in the ep0csr register. the function controller use this register's value to decode usb token packet address. at reset, if the device is not yet configured the value is reset to 0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 usb function address register (faddr) f0h, r/w not used for s3c9644/c9648/p9648 7-bit programming device address. this register maintains the usb address assigned by the host. the function controller uses this register?s value to decode usb token packet address. at reset when the device is not yet configured the value is reset to 0. figure 11-2. usb function address register (faddr)
s3c9644/c9648/p9648 universal serial bu s 11- 5 control endpoint control status register (ep0csr) ep0csr register controls endpoint 0 (control endpoint), and also holds status bits for endpoint 0. ep0csr is located at f1h and is read/write addressable. bit7 clear_setup_end: mcu writes ?1? to this bit to clear setup_end bit (bit4). this bit is automatically cleared after writing "1" by usb block. bit6 clear_out_pkt_rdy: mcu writes ?1? to this bit to clear out_pkt_rdy bit (bit0). this bit is automatically cleared after writing "1" by usb block. bit5 send_stall: mcu writes ?1? to this bit to send stall signal to the host, at the same time it clears out_pkt_rdy (bit0), if it decodes an invalid token. usb issues a stall handshake to the current control transfer. this bit gets cleared once a stall handshake is issued to the current control transfer. bit4 setup_end: usb sets this bit, when a control transfer ends before data_end bit (bit3) is set. mcu clears this bit, by writing a ?1? to clear_setup_end bit (bit7). when usb sets this bit, an interrupt is generated to mcu. when such condition occurs, usb flushes the fifo, and invalidates mcu?s access to fifo. bit3 data_end: mcu sets this bit: ? after loading the last packet of data into the fifo, and at the same time in_pkt_rdy bit is set. ? while it clears out_pkt_rdy bit after unloading the last packet of data. ? for a zero length data phase, when it clears out_pkt_rdy bit, and sets in_pkt_rdy bit. bit2 sent_stall: usb sets this bit, if a control transaction has ended due to a protocol violation. an interrupt is generated when this bit gets set. mcu clears this bit to end the stall condition. bit1 in_pkt_rdy: mcu sets this bit, after writing a packet of data into endpoint 0 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit so that mcu can load the next packet. for a zero length data phase, mcu sets in_pkt_rdy bit and data_end bit at the same time. bit0 out_pkt_rdy: usb sets this bit, once a valid token is written to fifo. an interrupt is generated, when usb sets this bit. mcu clears this bit by writing "1? to clear_out_pkt_rdy bit. in control transfer case, where there is no data phase, mcu after unloading the setup token, sets in_pkt_rdy, and data_end at the same time it clears out_pkt_rdy for the setup token. when setup_end bit is set, out_pkt_rdy bit may also be set. this happens when the current transfer has ended, and a new control transfer is received before mcu can service the interrupt. in such case, mcu should first clear setup_end bit, and then start servicing the new control transfer.
universal serial bus s3c9644/c9648/p964 8 11- 6 msb lsb .7 .6 .5 .4 .3 .2 .1 .0 clear_ setup_end clear_ out_pkt_rdy send_stall setup_end data_end sent_stall out_pkt_rdy in_pkt_rdy control endpoint status register (ep0csr) f1h, r/w figure 11-3. control endpoint status register (ep0csr)
s3c9644/c9648/p9648 universal serial bu s 11- 7 interrupt endpoint 1 control status register (ep1csr) ep1csr is the control register for endpoint 1, interrupt endpoint. this register is located at address f2h and is read/write addressable. bit7 clear_data_toggle: mcu writes ?1? to this bit to clear the data toggle sequence bit. when the mcu writes a 1 to this register, the data toggle bit is initialized to data0. bit6-3 maxp: these bits indicate the maximum packet size for in endpoint, and needs to be updated by mcu before it sets in_pkt_rdy. once set, the contents are valid till mcu re-writes them. bit2 flush_fifo: when mcu writes ?1? to this register, the fifo is flushed, and in_pkt_rdy cleared. the mcu should wait for in_pkt_rdy to be cleared for the flush to take place. bit1 force_stall: mcu writes ?1? to this register to issue a stall handshake to usb. mcu clears this bit, to end the stall condition. bit0 in_pkt_rdy: mcu sets this bit, after writing a packet of data into endpoint 1 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit, so mcu can load the next packet. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 clear_data_toggle maxp flush_fifo in_pkt_rdy force_stall control endpoint status register (ep1csr) f2h, r/w figure 11-4. 1 interrupt endpoint 1 status register (ep1csr)
universal serial bus s3c9644/c9648/p964 8 11- 8 interrupt endpoint 2 control status register (ep2csr) ep2csr is the control register for endpoint 2, interrupt endpoint. this register is located at address f9h and is read/write addressable. bit7 clear_data_toggle: mcu writes ?1? to this bit to clear the data toggle sequence bit. when the mcu writes a 1 to this register, the data toggle bit is initialized to data0. bit6-3 maxp: these bits indicate the maximum packet size for in endpoint, and needs to be updated by mcu before it sets in_pkt_rdy. once set, the contents are valid till mcu re-writes them. bit2 flush_fifo: when mcu writes ?1? to this register, the fifo is flushed, and in_pkt_rdy cleared. the mcu should wait for in_pkt_rdy to be cleared for the flush to take place. bit1 force_stall: mcu writes ?1? to this register to issue a stall handshake to usb. mcu clears this bit, to end the stall condition. bit0 in_pkt_rdy: mcu sets this bit, after writing a packet of data into endpoint 1 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit, so mcu can load the next packet. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 clear_data_toggle maxp flush_fifo in_pkt_rdy force_stall control endpoint status register (ep2csr) f9h, r/w figure 11-5. 2 interrupt endpoint status register (ep2csr) control endpoint byte count register (ep0bcnt) ep0bcnt register has the number of valid bytes in endpoint 0 fifo. it is located at address f3h read-only addressable. once the mcu receives a out_pkt_rdy (bit0 of ep0csr) for endpoint 0, then it can read this register to find out the number of bytes to be read from endpoint 0 fifo.
s3c9644/c9648/p9648 universal serial bu s 11- 9 control endpoint fifo register (ep0fifo) this register is bi-directional, 8-byte depth fifo used to transfer control endpoint data. ep0fifo is located at address f4h and is read/write addressable. initially, the direction of the fifo, is from the host to the mcu. after a setup token is received for a control transfer, that is, after mcu unload the setup data packet, and clears out_pkt_rdy, the direction of fifo is changed automatically by the direction bit of data packet. interrupt endpoint 1 fifo register (ep1fifo) ep1fifo is an uni-direction 8-byte depth fifo used to transfer data from the mcu to the host. mcu writes data to this register, and when finished set in_pkt_rdy. this register is located at address f5h. interrupt endpoint 2 fifo register (ep2fifo) ep1fifo is an uni-direction 8-byte depth fifo used to transfer data from the mcu to the host. mcu writes data to this register, and when finished set in_pkt_rdy. this register is located at address fah.
universal serial bus s3c9644/c9648/p964 8 11- 10 usb interrupt pending register (usbpnd) usbpnd register has the interrupt bits for endpoints and power management. this register is cleared once read by mcu. while any one of the bits is set, an interrupt is generated. usbpnd is located at address f6h. bit7-4 not used bit4 endpt2_pnd: this bit is set, when endpoint 2 needs to be serviced. bit3 resume_pnd: while in suspend mode, if resume signaling is received this bit gets set. bit2 suspend_pnd: this bit is set, when suspend signaling is received. bit1 endpt1_pnd: this bit is set, when endpoint 1 needs to be serviced. bit0 endpt0_pnd: this bit is set, when endpoint 0 needs to be serviced. it is set under any one of the following conditions: ? out_pkt_rdy is set. ? in_pkt_rdy gets cleared. ? sent_stall gets set. ? data_end gets cleared. ? setup_end gets set. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 usb interrupt pending register (usbpnd) f6h, r/w not used resume_pnd suspend_pnd endpt0_pnd endpt1_pnd endpt2 _pnd figure 11-6. usb interrupt pending register (usbpnd)
s3c9644/c9648/p9648 universal serial bu s 11- 11 usb interrupt enable register (usbint) usbint is located at address f7h and is read/write addressable. this register serves as an interrupt mask register. if the corresponding bit = 1 then the respective interrupt is enabled. by default, all interrupts except suspend interrupt is enabled. interrupt enables bits for suspend and resume is combined into a single bit (bit 2). bit7-3 not used bit3 enable_endpt2_int: 1 enable endpoint 1 interrupt (default) 0 disable endpoint 1 interrupt bit2 enable_suspend_resume_int: 1 enable suspend and resume interrupt 0 disable suspend and resume interrupt (default) bit1 enable_endpt1_int: 1 enable endpoint 1 interrupt (default) 0 disable endpoint 1 interrupt bit0 enable_endpt0_int: 1 enable endpoint 0 interrupt (default) 0 disable endpoint 0 interrupt msb lsb .7 .6 .5 .4 .3 .2 .1 .0 usb interrupt enable register (usbint) f7h, r/w not used enable_suspend_resume_int enable_endpt1_int enable_endpt0_int enable_endpt2_int figure 11-7. usb interrupt enable register (usbint)
universal serial bus s3c9644/c9648/p964 8 11- 12 usb power management register (pwrmgr) pwrmgr register interacts with the host?s power management system to execute system power events such as suspend or resume. this register is located at address f8h and is read/write addressable. bit7-2 reserved: the value read from this bit is zero. bit1 send_resume: while in suspend state, if the mcu wants to initiate resume, it writes ?1? to this register for 10ms (maximum of 15 ms), and clears this register. in suspend mode if this bit reads ?1?, usb generates resume signaling. bit0 suspend_state: suspend state is set when the mcu sets suspend interrupt. this bit is cleared automatically when: ? mcu writes ?0? to send_resume bit to end the resume signaling (after send_resume is set for 10 ms). ? mcu receives resumes signaling from the host while in suspend mode. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 usb power management register (pwrmgr) f8h, r/w the value read form this bit is zero send_resume suspend_state figure 11-8. usb power management register (pwrmgr)
s3c9644/c9648/p9648 universal serial bu s 11- 13 usb mode select register (usbsel) usbsel is located at address fbh and is read/write addressable. this register serves as an usb mode and ps2 mode. bit7-1 not used bit0 usbsel: 0 = ps2 mode. (default) 1 = usb mode. (this bit is set when the d+/ps2, d-/ps2 port set the d+, d-) msb lsb .7 .6 .5 .4 .3 .2 .1 .0 usb mode select register (usbsel) fbh, r/w not used usbsel figure 11-9. usb mode select register (usbsel)
universal serial bus s3c9644/c9648/p964 8 11- 14 usb reset register (usbrst) usbrst register receives a reset signal from the host. this register is located at address ffh and is read/write addressable. bit7-1 not used bit0 usbrst: this bit is set when the host issues an usb reset signal. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 usb reset register (usbrst) ffh, r/w not used usbrst figure 11-10. usb reset register (usbrst)
s3c9644/c9648/p9648 electrical data 12- 1 12 electrical data overview in this section, the following s3c9644/c9648/p9648 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? inp ut/output capacitance ? a.c. electrical characteristics ? input timing for external interrupt (ports 0, 2 and 4) d+/ps2, d-/ps2 : ps2 mode only ? input timing for reset ? oscillator characteristics ? oscillation stabilization time ? clock timing measurement points at x in ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? stop mode release timing when initiated by an external interrupt ? characteristic curves
electrical data s3c 9644/c9648/p9648 12- 2 table 12-1. absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in all input ports ? 0.3 to v dd + 0.3 v output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 3 + 100 total pin current for ports 0, 1, 2, 4 + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c
s3c9644/c9648/p9648 electrical data 12- 3 table 12-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c , v dd = 4.0 v to 5.25 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 6 mhz (instruction clock = 1 mhz) 4.0 5.0 5.25 v input high voltage v ih1 all input pins except v ih2 0.8 v dd ? v dd v v ih2 x in v dd ? 0.5 v dd v ih3 reset 0.5v dd input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v v il2 x in 0.4 v il2 reset 0.5v dd output high voltage v oh i oh = ? 200 a; all output ports except ports 0, 1 and 2, d+, d? v dd ? 1.0 ? ? v output low voltage v ol i ol = 1 ma all output port except d+, d? ? ? 0.4 v output low current i ol v ol = 3v port 3 only 8 15 23 ma input high leakage current i lih1 (3) v in = v dd all inputs except i lih2 except d+, d? ? ? 3 a i lih2 (3) v in = v dd x in, x out, reset ? ? 20 a input low leakage current i lil1 (3) v in = 0 v all inputs except i lil2 except d+, d? ? ? ? 3 a i lil2 (3) v in = 0 v x in, x out, reset ? ? ? 20 a
electrical data s3c 9644/c9648/p9648 12- 4 table 12-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c , v dd = 4.0 v to 5.25 v) parameter symbol conditions min typ max unit output high leakage current i loh (1) v out = v dd all i/o pins and output pins except d+, d? ? ? 3 a output low leakage current i lol (1) v out = 0 v all i/o pins and output pins except d+, d? ? ? ? 3 a pull-up resistors r l1 v in = 0 v ports 0, 1, 2, 4.2-3, reset 25 50 100 k w r l2 v in = 0 v; p4.0-1 2.4 supply current (2) i dd1 normal operation mode 6 mhz cpu clock ? 5.5 12 ma i dd2 idle mode; 6 mhz oscillator 2.2 5 ma i dd3 stop mode 180 300 a notes: 1. except x in and x out . 2. supply current does not include current drawn through internal pull-up resistors or external output current loads. 3. when usb mode only in 4.2 v to 5.25 v, d+ and d? satisfy the usb spec 1.0.
s3c9644/c9648/p9648 electrical data 12- 5 table 12-3. input/output capacitance (t a = ? 40 c to + 85 c , v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 12-4. a.c. electrical characteristics (t a = ? 40 c to + 85 c , v dd = 4.0 v to 5.25 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl p0, p2 and p4 ? 200 ? ns reset input low width t rsl reset 10 ? ? m s t intl t inth 0.8 v dd 0.2 v dd figure 12-1. input timing for external interrupt (ports 0, 2, and 4) reset t rsl 0.5v dd figure 12-2. input timing for reset
electrical data s3c 9644/c9648/p9648 12- 6 table 12-5. oscillator characteristics (t a = ? 40 c + 85 c , v dd = 4.0 v to 5.25 v) oscillator clock circuit test condition min typ max unit main crystal main ceramic (f osc ) c2 x in x out c1 oscillation frequency ? 6.0 ? mhz external clock x in x out oscillation frequency ? 6.0 ? table 12-6. oscillation stabilization time (t a = ? 40 c + 85 c , v dd = 4.0 v to 5.25 v) oscillator test condition min typ max unit main crystal f osc = 6.0 mhz ? ? 10 ms main ceramic (oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range.) oscillator stabilization wait time t wait stop mode release time by a reset ? 2 16 / f osc ? t wait stop mode release time by an interrupt ? (note) ? note: the oscillator stabilization wait time, t wait , is determined by the setting in the basic timer control register, btcon.
s3c9644/c9648/p9648 electrical data 12- 7 table 12-7. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c ) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 6 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? ? 300 a t xl t xh v dd 0.5v 0.4v x in 1/f osc figure 12-3. clock timing measurement points at x in
electrical data s3c 9644/c9648/p9648 12- 8 t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset oper a tion idle mode (basic timer active) 0.5 v dd 0.5 v dd normal operating mode ~ ~ ~ ~ ~ ~ ~ ~ figure 12-4. stop mode release timing when initiated by a reset t wait v dd external interrupt execution of stop instruction v dddr data retention mode stop mode idle mode (basic timer active) 0.8 v dd 0.2 v dd normal operating mode ~ ~ ~ ~ ~ ~ ~ ~ figure 12-5. stop mode release timing when initiated by an external interrupt
s3c9644/c9648/p9648 electrical data 12- 9 table 12-8. low speed usb electrical characteristics (t a = ? 40 c to + 85 c, voltage regulator output v 33out = 2.8 v to 3.5 v, typ 3,3 v) parameter symbol conditions min max unit transition time: rise time tr cl = 50 pf 75 ? ns cl = 350 pf ? 300 fall time tf cl = 50 pf 75 ? cl = 350 pf ? 300 rise/fall time matching trfm (tr/tf) cl = 50 pf 80 120 % output signal crossover voltage vcrs cl = 50 pf 1.3 2.0 v voltage regulator output voltage v33out with v33out to gnd 0.1 m f capacitor 2.8 3.5 v measurement points 90% 90% tr tf 1 0% d.u.t r1 s/w 2.8v test point cl r1 = 15 k w r2 = 1.5 k w cl = 50pf-350pf dm: s/w on dp: s/w off r2 1 0% figure 12-6. usb data signal rise and fall time vcrs max: 2.0 v min : 1.3 v 3.3 v 0 v dp dm figure 12-7. usb output signal crossover point voltage
s3c9644/c9648/p9648 mechanical data 13- 1 13 mechanical data overview the s3c9644/c9648/p9648 is available in a 42-pin sdip package (samsung: 42-sdip-600) and a 44-pin qfp package (44 -qfp-1010b). package dimensions are shown in figures 13-1 and 13-2. 0-15 15.24 0.25 +0.1 ? 0.05 0.51min 3.50 0.2 3.30 0.3 5.08max 39.10 0.2 39.50 max 1.00 0.1 0.50 0.1 (1.77) 1.778 14.00 3 0.2 #1 #21 #42 #22 40-sdip-600 figure 13-1. 42-pin sdip package mechanical data (42-sdip-600 )
mechanical data s3c 9644/c9648/p9648 13- 2 note : dimensions are in millimeters. 44-qfp-1010b 13.20 0.3 #44 (1.00) #1 13.20 0.3 10.00 0.2 0.35 +0.10 - 0.05 0.10 max 0.15 +0.10 - 0.05 0 - 8 0.05 min 2.05 0.10 2.30 max 0.80 0.20 0.80 10.00 0.2 figure 13-2. 44-pin qfp package mechanical data (44-qfp-1010b)
s3c9644/c9648/p9648 S3P9648 otp 14- 1 14 S3P9648 otp overview the S3P9648 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c9644/c9648 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P9648 is fully compatible with the s3c9644/c9648, both in function and in pin configuration. because of its simple programming requirements, the S3P9648 is ideal for use as an evaluation chip for the s3c9644/c9648. p3.1 p3.0 int0 / p2.0 int0 / p2.1 int0 / p2.2 int0 / p2.3 int0 / p2.4 int0 / p2.5 sdat /int0 / p2.6 sclk / int0 / p2.7 v dd / v dd v ss /v ss x out / x out x in /x in test /test int1 / p4.0 int1 / p4.1 reset reset / reset int1 / p4.2 int1 / p4.3 p1/7 S3P9648 42-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.2 p3.3/clo d+ d- 3.3 v out nc p0.0 / int2 p0.1 / int2 p0.2 / int2 p0.3 / int2 p0.4 / int2 p0.5 / int2 p0.6 / int2 p0.7 / int2 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 14-1. S3P9648 pin assignments (42-sdip package)
S3P9648 otp s3c9644/c9648/p9648 14- 2 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p4.3/int1 p4.2/int1 reset/ reset reset 3.3 v out d-/ps2 d+/ps2 p3.3/clo p3.2 p3.1 p3.0 p2.0/int0 p2.1/int0 p2.2/int0 p2.3/int0 nc nc nc p0.0/int2 p0.1/int2 p0.2/int2 p0.3/int2 p0.4 /int2 p0.5/int2 p0.6/int2 p0.7/int2 p2.4/int0 p2.5/int0 p2.6/int0/ sdat p2.7/int0/ sclk v dd/ v dd v ss/ v ss x out/ x out x in/ x in test/ test p4.0/int1 p4.1/int1 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 s3c9648 44-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 figure 14-2. S3P9648 pin assignments (44-qfp package)
s3c9644/c9648/p9648 S3P9648 otp 14- 3 table 14-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p2.6 sdat 9 (3) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p2.7 sclk 10 (4) i/o serial clock pin (input only pin) test test 15 (9) i chip initialization and eprom cell writing power supply pin (indicates otp mode entering) when writing 12.5 v is applied and when reading. reset reset 18 (12) i 0 v: otp write and test mode 5 v: operating mode v dd / v ss v dd / v ss 11 (5) /12 (6) ? logic power supply pin. note: ( ) means 44 qfp package. table 14-2. comparison of S3P9648 and s3c9644/c9648 features characteristic S3P9648 s3c9644/c9648 program memory 8-kbyte eprom 8-kbyte mask rom operating voltage (v dd ) 4.0 v to 5.25 v 4.0 v to 5.25 v otp programming mode v dd = 5 v, v pp (reset) = 12.5 v pin configuration 42 sdip/44 qfp 42 sdip/44 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (reset) pin of the S3P9648, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 14-3 below. table 14-3. operating mode selection criteria v dd vpp ( reset ) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
S3P9648 otp s3c9644/c9648/p9648 14- 4 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 14-3. otp programming algorithm
s3c9644/c9648/p9648 S3P9648 otp 14- 5 table 14-4. d.c. electrical characteristics (t a = ? 40 _ c to + 85 _ c, v dd = 4.0 v to 5.25 v) parameter symbol conditions min typ max unit supply current (note) i dd1 normal mode; 6 mhz cpu clock ? 5.5 12 ma i dd2 idle mode; 6 mhz cpu clock 2.2 5 i dd3 stop mode 180 300 a note: supply current does not include current drawn through internal pull-up resistors or external output current loads.
s3c9644/c9648/p9648 development tools 15- 1 15 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c8, s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9-series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value "ff" is filled into the unused rom area upto the maximum rom size of the target device automatically.
development tools s 3c9644/c9648/p9648 15- 2 target boards target boards are available for all s3c9-series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one times programmable microcontrollers (otps) are under development for s3c9644/c9648 microcontroller. bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9648 target board eva chip target application system figure 15-1. smds product configuration (smds2+)
s3c9644/c9648/p9648 development tools 15- 3 tb9648 target board the tb9648 target board is used for the s3c9644/c9648 microcontrollers. it is supported by the smds2+ development systems. the tb9648 target board can also be used for s3c9644/c9648. 25 tb9648 sm1306a to user_vcc off on 1 cn1 100-pin connector reset vcc gnd u1 + stop + idle 21 30-pin dip socket j101 20 1 40 144 qfp s3e9600 eva chip 30 1 smds2+ smds2 external triggers ch1 ch2 figure 15-2. tb9648 target board configuration
development tools s 3c9644/c9648/p9648 15- 4 table 15-1. power selection settings for tb9648 'to user_vcc' settings operating mode comments to user_vcc on off tb9648 target system v ss v cc smds2+ v cc external the smds2/smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off external tb9648 target system vcc v ss v cc smds2+ the smds2/smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note: the following symbol in the "to user_v cc " setting column indicates the electrical short (off) configuration: smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 15-2. the smds2+ tool selection setting "sw1" setting operating mode smds2+ smds2 smds2+ target board r/w* r/w*
s3c9644/c9648/p9648 development tools 15- 5 table 15-3. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system a you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions.
development tools s 3c9644/c9648/p9648 15- 6 4 0 -pin connector p3.1 p3.0 int0/p2.0 int0/p2.1 int0/p2.2 int0/p2.3 int0/p2.4 int0/p2.5 int0/p2.6 int0/p2.7 v dd v ss1 v ss int1/p4.0 int1/p4.1 reset int1/p4.2 int1/p4.3 p1.7 p1.6 p3.2 p3.3/clo d+ d- 3.3 v out v ss2 p0.0/int2 p0.1/int2 p0.2/int2 p0.3/int2 p0.4/int2 p0.5/int2 p0.6/int2 p0.7/int2 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 j101 figure 15-3. 40-pin connector for tb9648 20 4 0-pin connector target board part name: ap42sd-j order code: sm6524 j101 1 40 20 21 1 42 21 22 42 sdip conversion pcb j101 target system 40 1 21 figure 15-4. s3c9648 probe adapter cable for 42-sdip package

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